Dual mode class D amplifiers

ABSTRACT

A circuit for avoiding AM radio interference in a class D amplifier includes comparing means that compares the frequency of an AM signal to one or more reference signals. The comparing means generates comparator signals indicative of whether the first signal is greater than, less than or equal to the reference signals. A frequency divisor signal that represents a frequency divisor number is issued dependent at least in part upon the comparator signals. Dividing means generate an oscillator signal for the class D amplifier that has a frequency derived by dividing the frequency of the AM signal by the frequency divisor number.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. patent applicationSer. No. 09/342,376, filed Jun. 29, 1999, which in turn claims thebenefit of U.S. Provisional Patent Application Ser. No. 60/113,197 filedDec. 22, 1998.

FIELD OF THE INVENTION

[0002] The present invention relates generally to class D amplifiersand, more particularly, to class D amplifiers that have one or moremodes of operation for avoiding AM radio harmonic frequencies duringoperation.

BACKGROUND OF THE INVENTION

[0003] Class D power amplifiers are typically pulse-width modulatedamplifiers that switch at frequencies well above the top of the audioband, often at frequencies of 100 kHz or greater. When a class Damplifier switches at these high frequencies, the switching frequency orits harmonics can interfere with AM radio receivers that are locatedclose to the class D amplifier. Because of these interference problems,class D amplifiers cannot be easily integrated into consumer electronicproducts, such as stereo receivers, that have an AM tuner and poweramplifier in the same chassis. Class D modulators switching in the 50khz to 2 MHz range generate harmonics which interfere with AM radioreception. This has precluded wide spread acceptance of class D inproducts with an AM radio.

[0004] The AM radio broadcast band spans from 540 to 1700 kHz in the USand up to 30 MHz worldwide. To sample a 20 khz audio signal, class Dmodulators must run at frequencies greater than 200 khz. Because theoutput of these modulators is a pulse width modulated square wave, themodulators generate both even and odd harmonics. The low pass filterthat removes the carrier from the speaker leads also attenuates theseharmonics. However, it is not practical to design a filter with adequatehigh frequency attenuation and still pass 20 kHz audio signals withoutinterfering with the sensitive AM receiver bandpass. Furthermore, theprinted circuit board traces carrying the pulse width modulated squarewave tend to radiate radio frequency energy that may be picked up by theAM antenna.

[0005] In theory the problem can be solved by ensuring the clockfrequency of the class D modulator is much higher than the AM broadcastband. This however cannot be practically implemented for severalreasons. First, with a 2 MHz carrier the FETs must be switched by highcurrent gate drivers. At the duty cycle extremes, the very short on andoff times are not possible to achieve even with high gate drive. Thus,the theoretical power is limited. Secondly, the fast switching timeswill make it nearly impossible to achieve EMC compliance above 30 Mhz.Further, unless all the clocks are synchronized in stereo and fivechannel applications, IMD products will be generated that will interferewith the AM band. Moreover, the body diodes of the MOSFETS have arelatively long recovery time, and thus cannot be used at this highfrequency. Thus, a Shottky commutating diode is required. At busvoltages greater than 48 VDC, the forward drop of this diode may behigher than that of the body diode, and the body diode will have to beblocked with a drain diode. Lastly, the AM band in Europe extends to 30Mhz.

SUMMARY OF THE INVENTION

[0006] The present invention provides, in one form thereof, circuits andmethods for solving the problem of class D amplifier interference withthe AM radio band. In its broader aspects the invention provides one ormore reference standards for frequency. The AM radio's local oscillatorsignal, or the switching amplifier signal, or both, are compared to thestandards. Suitable circuitry then modifies the switching amplifiersignal to keep the switching amplifier signal far enough away from thetuned AM radio station and the local oscillator and thereby avoid theproblem of interference. The invention provides means for monitoring thelocal oscillator and the switching signal and selecting a switchingoscillator signal that has a frequency which is neither a harmonic ofthe local oscillator nor the tuned AM radio station. The inventioneither generates the switching signal from the local oscillator orselects another oscillator with a frequency that is not a harmonic ofthe local oscillator or tuned AM radio station.

[0007] The class D amplifier controlled by the divided local oscillatorsignal in each of these embodiments may be any suitable amplifier,including a self oscillating pulse width modulator with an integratorwith feedback from the output of the amplifier and a comparator coupledto the output of the integrator. The output of the modulator is coupledto a bridge gate driver that controls the power to a MOSFET bridgecircuit. The bridge circuit is connected between high and low voltagepower busses and has at least two MOSFETs connected in series with eachother. The class D amplifier under discussion must have a provision forexternal control of its switching frequency.

[0008] The local oscillator signal is present in all AM radios and is ata frequency of 450 or 455 kHz above the tuned radio station in radiosdesigned to receive the US broadcast band. The local oscillator may befound at different offsets from the tuned station in other nations, buta circuit can be designed as long as the offset is known. The localoscillator can take any periodic form depending on the design of thetuner. Often the local oscillator is a sine wave created by aphase-locked loop circuit.

[0009] Those skilled in the art understand that the control conceptdescribed in the analog comparator embodiment can be implemented byusing any of a very large number of physical products, including, butnot limited to, digital devices such as Complex Programmable LogicDevices (CPLDs), Field Programmable Gate Arrays (FPGAs),microcontrollers, semi-custom or custom Application Specific IntegratedCircuits (ASICs), and 74xxxx series integrated circuit logic gates. Alarge number of different analog devices, including resistors,capacitors, inductors, transistors, and field-effect transistors (FETs)may be combined in different ways to implement the analog portion of thealgorithm presented here. Future technological advances may produceother physical devices capable of implementing the algorithm. Regardlessof the products used for implementation of this algorithm, anyimplementation of the algorithm is covered in this patent.

[0010] Analog Comparators

[0011] One embodiment of the invention uses analog comparators and adigital counter. That embodiment takes a local oscillator signal fromthe AM tuner and uses it to intelligently determine a fixed operatingfrequency for a class D amplifier. The local oscillator is divided by aninteger number N where 2<N<7 for the US AM broadcast band and theparticular class D amplifier for which the system was devised. N variesbetween three and six inclusive throughout the range of local oscillatorfrequencies used in an AM tuner. N for any particular local oscillatorfrequency is chosen so that the frequency and its harmonics resultingfrom dividing the local oscillator frequency by N are as far as possiblefrom the tuned radio station corresponding to the frequency of the localoscillator.

[0012] The analog comparator embodiment provides a method fordetermining the appropriate value of N based on a pre-determinedalgorithm. The method is comprised of a set of analog voltagecomparators that control a digital divide-by-N circuit. The divide-by-Ncircuit divides the frequency of the AM local oscillator pulse train bythe appropriate value of N.

[0013] Digital Comparators

[0014] Another embodiment of the invention relies upon a square waveinput oscillator signal and a digital circuit for dividing the squarewave to a non-interfering frequency. That embodiment takes a localoscillator signal from the AM tuner and uses it to intelligentlydetermine a fixed operating frequency for a class D amplifier. The localoscillator is divided by an integer number N where 2<N<7 for the US AMbroadcast band in the particular application of this control methodpresented here. N will vary from three to six throughout the range oflocal oscillator frequencies used in an AM tuner. N is chosen so thatthe frequency and its harmonics resulting from dividing the localoscillator frequency by N are as far as possible from the tuned radiostation corresponding to the frequency of the local oscillator. Keepingthe switching harmonics and fundamental away from the tuned radiostation's frequency and the local oscillator prevents electromagneticinterference.

[0015] The digital comparator embodiment providing a method fordetermining the appropriate value of N is described in this document.The method is essentially a digital window comparator comprised of acounter and a latch that serves as an input to three digital magnitudecomparators. The magnitude comparators instruct a divide-by-N circuit onthe proper value of N by which to divide the local oscillator.

[0016] The class D amplifier under discussion must have a provision forexternal control of its switching frequency. Such an amplifier with anexternal input would be controlled by the algorithm described in thispatent.

[0017] Two Loop

[0018] A third embodiment is a two loop digital comparator circuit. Ittakes a local oscillator signal from the AM tuner and uses it tointelligently determine a fixed operating frequency for a class Damplifier. The local oscillator is divided by an integer number N where,for the particular amplifier used, 2<N<7 for the US AM broadcast band. Nvaries throughout the range of local oscillator frequencies used in anAM tuner. N is chosen so that the frequency and its harmonics resultingfrom dividing the local oscillator frequency by N are as far as possiblefrom the tuned radio station corresponding to the frequency of the localoscillator.

[0019] An algorithm for determining the appropriate value of N isdescribed in this document. The algorithm is essentially a pair offrequency comparators that compare the local oscillator frequency withboth a maximum frequency and a previously detected frequency. Thefrequency comparators instruct a divide-by-N circuit on the proper valueof N by which to divide the local oscillator.

[0020] The class D amplifier under discussion must have a provision forexternal control of its switching frequency. Such an amplifier with anexternal input would be controlled by the algorithm described in thispatent.

[0021] Selected Clocks

[0022] A fourth embodiment relies upon selecting one of a plurality ofclocks or oscillators based upon a comparison of the local oscillator tothe switching frequency of the class D amplifier. It provides a circuitand a method that prevents electromagnetic interference from class Damplifiers from interfering with AM radios located in the same chassisas the class D amplifiers. The method can be used in a variety ofconsumer electronic audio products such as AM/FM stereo receivers,portable “boom boxes,” and personal stereos such as the Sony Walkman. Anelectronic controller has been developed that controls the switchingfrequency of a class D amplifier to prevent its switching fundamentaland harmonics from interfering with the in-chassis AM radio.

[0023] The class D amplifier under discussion must have a provision forexternal control of its switching frequency. Such an amplifier with anexternal input would be controlled by the algorithm described in thispatent.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1 is a schematic of a typical prior art class D amplifier;

[0025]FIG. 2 is a schematic diagram of a dual mode harmonic avoidanceclass D amplifier;

[0026]FIG. 3 is a schematic diagram of a dual mode combined class D/ABamplifier;

[0027]FIG. 4 is a block diagram of a method for using the AM localoscillator as a clock source for a class D amplifier;

[0028]FIG. 5 is a block diagram of a method for using the AM localoscillator as a clock source for a class D amplifier;

[0029]FIG. 6 is a block diagram of an algorithm for dividing the AMlocal oscillator down to a frequency usable by a suitable class Damplifier; and

[0030]FIG. 7 is a block diagram of a method for using the AM localoscillator as a reference for making intelligent control decisions aboutthe switching frequency of a class D amplifier that does not interferewith a nearby AM radio.

DETAILED DESCRIPTION OF THE DRAWINGS

[0031] Advances in MOSFET technology as well as advances in integratedcircuits have made it possible to apply class D amplifiers to audioapplications. Class D amplifiers are significantly more efficient thanclass AB amplifiers. In the past, disadvantages of class D amplifiersincluded higher parts count, cost, electromagnetic interference, andpoor performance. With increased integration and the introduction ofsophisticated control integrated circuits these disadvantages arebecoming less pronounced. In the near future, class D amplifiers willreplace class AB amplifiers in many applications. Class D amplifiersalready have a clear advantage in high power applications. As the costand component count of these amplifiers fall, class D amplifiers will beable to complete with class AB amplifiers in low and medium powerapplications.

[0032] To overcome the poor performance of class D amplifiers, othershave suggested a self oscillating variable frequency modulator as shownin FIG. 1. An integrator 10 has an audio input over an input resistorR_(IN). It has a digital feedback input A over resistor R_(DFB), and ananalog feedback at input B over resistor R_(AFB). The respective analogand digital feedback signals A, B, are taken from the output of thebridge circuit 20 and the low-pass filter that comprises the inductor Land capacitor C_(LP). For purposes of understanding, let us simply focuson the digital output A and assume that there is no audio input. In thiscase, the output at point A is a square wave with a 50% duty cycle. Whenthe square wave is high, current flows through R_(DFB) into the summingjunction of the integrator 10. Its output ramps down until it reachesthe negative threshold of the comparator 12. R1 and R2 are used to addhysteresis to the comparator 12. These resistors can be used to adjustthe comparator positive and negative thresholds. When the output of thecomparator 12 goes low, the upper FET 22 turns off and after a shortdelay the lower FET 24 turns on. The square wave goes low, and currentnow flows out of the integrator 10 summing junction through R_(DFB). Theoutput of the integrator 10 reverses and ramps up until it reaches thepositive threshold of the comparator 12. This signals the lower FET 24to turn off and after a short delay the upper FET 22 turns on. Thesquare wave goes high and the cycle continues. With no audio signal, theoutput at A is a 50% square wave, and the output of the integrator 10 isa triangle wave.

[0033] Now consider the case when an audio signal is applied. Assumingthat the audio signal is positive, then current flows through R_(IN)into the integrator summing junction. Current also flows through R_(AFB)out of the summing junction (negative feedback). The net contribution ofthe audio signal to the integrator summing junction current isI_(RIN)−I_(RAFB). When the upper FET 22 is on, the currents I_(DFB) and(I_(RIN)−I_(RAFB)) are both into the summing junction. This speeds upthe ramp at the output of the integrator 10. When the lower FET 24 ison, the current through I_(DFB) reverses and the two current now are inopposite directions. This slows the ramp down. A similar analysis can beapplied to the case where the input signal is negative.

[0034] Since the hysteresis built into the comparator 12 is constant,the slope of the positive and negative ramps directly affects thepositive and negative pulse widths, and therefore the duty cycle andfrequency of the comparator output. At the higher positive audio inputvoltages, the audio output becomes negative and the on time of the highside switch becomes negligible compared to the on time period of the lowside switch. The width of the low side pulse is roughly proportional tothe output voltage and primarily sets the loop frequency.

[0035] Harmonic Avoidance Class D Amplifier

[0036] Sonic performance is very important in audio amplifiers. Audioclass D amplifiers must have low THD, low noise, and a flat frequencyresponse. These performance specifications conflict with the requirementthat the amplifier must not interfere with AM radio. The solution isdual mode operation. When in an AM-compatibility mode, the amplifiermust not interfere with AM radio reception. Since AM radio is bandlimited to 5 khz and the background noise is high, a slight degradationin performance is acceptable in most cases. Otherwise, the design goalis to optimize the sound for maximum fidelity.

[0037]FIG. 2 shows one solution that includes a harmonic avoidanceamplifier. The local oscillator signal for an AM receiver is 450 KHzabove the selected receive frequency. This signal provides theinformation necessary for the harmonic avoidance circuit to know whatfrequency to avoid. It also provides a frequency standard to which tosynchronize multiple amplifiers to prevent intermodulation of individualamplifier clocks that could produce interference at the selectedfrequency.

[0038] This amplifier solves the AM interference issue by preventingco-location of clock harmonics with the receiver-selected frequency. FMinterference can be solved with appropriate filtering, shielding, andsoft switching techniques. This technique allows full power operationfor both AM and FM receptions with only a minor degradation of audioperformance in AM reception associated with the fixed frequencymodulator in AM compatibility mode. The concept of dual mode operationis not limited to this specific example. Dual mode operation can involveother techniques which control the harmonics generated by the switchingamplifier or other amplification technology when receiving AM signals.AM interference is the primary concern. Otherwise, audio fidelity is theprimary design goal.

[0039] Combined Class D/AB Amplifier

[0040]FIG. 3 shows one possible solution for a dual mode amplifier. Whenin AM mode, the two MOSFETS are controlled as a class AB amplifier.Otherwise, the amplifier operates as a class D amplifier.

[0041] The AM/FM switch 10 sets the mode of operation. The AM modedetector block, 1, generates a logic signal depending on the switch. IfAM-compatibility mode is engaged, then the amplifier operates as a classAB amplifier. The AM logic signal is applied to the two transmissiongates, 4, so that the class AB amplifier is connected directly to thegates of the MOSFETS. Meanwhile, the inverted AM signal tri-states bothgate drivers. Sensing the voltage drop across the two resistors, Re1 andRe2, provides current limit protection. When AM-compatibility mode isnot engaged, the amplifier operates as a class D amplifier. The twotransmission gates are open disconnecting the class AB from the gates.The inverted AM signal enables both gate drivers.

[0042] This amplifier solves the AM interference issue by operating as aclass AB amplifier while in AM-compatibility mode. FM interference canbe solved with appropriate filtering, shielding, and soft switchingtechniques. While the peak power is the same for both modes ofoperation, AM mode is limited by the poor efficiency of class ABamplifiers.

[0043] The concept of dual mode operation is not limited to the specificexample. In theory it can be extended to cover class A and class Blinear amplifiers. Furthermore, dual mode operation can involve othertechniques that control the harmonics generated by the switchingamplifier itself. This would allow the amplifier to switch between twohigh efficiency modes. In AM mode, AM interference is the primaryconcern. Otherwise, audio fidelity is the primary design goal.

[0044] Analog Comparators

[0045] A method for using the AM local oscillator (LO) as a clock sourcefor a class D amplifier is shown in FIG. 4. The local oscillator signal100 is fed through a filter 110 that may be either an active or passivecircuit. As long as the time constant for the filter is long enough,variations in the input local oscillator frequency will result in anearly-DC, very slowly changing output voltage 150 from the filter. Themagnitude of the output voltage varies with the frequency of the inputAM local oscillator voltage: the higher the input frequency, the higherthe output voltage and vice versa. The output voltage is fed to threeanalog hysteresis voltage comparator circuits 160,161,162. Thehysteresis characteristic keeps the comparators from rapidly changingstate and thus stabilizes the comparator outputs. Each comparator has adifferent reference voltage 120, 130, or 135 as its comparison point.The reference voltages are found using a predetermined algorithm thatdetermines the optimal points within the AM band at which to switch fromone value of N to another. The optimal points are based on the resultantswitching frequency's proximity to the tuned radio station, the maximumdesired switching frequencies (due to efficiency considerations), theminimum desired switching frequencies (based on audio frequencyfiltering considerations), and the frequency of the local oscillator(450 or 455 kHz). Those skilled in the art understand that the range offrequencies covered by the comparators and the algorithm varies with therange of the input AM frequencies and the frequency of the localoscillator.

[0046] Combinational logic 180 considers the states of the three analogcomparators and generates a three-bit value for N 190. N is a three bitbinary input to a digital divide-by-N circuit. Those skilled in the artunderstand that the combinational logic block 180 can be designed withmany different logic devices including AND, NAND, OR, and NOR gates.

[0047] A divide-by-N circuit 200 divides the frequency of LO input 100by N 190. The divided-down LO 210 is the resultant output. Those skilledin the art understand that the divide-by-N circuit can be created inmany different ways, including using integrated circuit divide-by-Nlogic devices, other off-the-shelf logic products, or gate-leveldesigns. The divided-down LO 210 is a fixed frequency square wavedependent upon the frequency of the LO 100. The divided-down LO 210 isused to control the frequency of an attached class D amplifier.

[0048] Here is an example of how the circuit and method works to providea class D oscillator signal that does not interfere with an input AMsignal. Assume the AM oscillator is at a frequency of 1200 kHz. Thefilter 110 is a passive circuit comprising a capacitor and resistors. Itconverts the 1200 kHz signal in to a 4 volt dc signal. The referencevoltage signals are 6 volts for reference A, 3 volts for reference B,and 1 volt for reference C. The comparators 160, 161, 162 are hysteresiscomparators. They output a binary signal of “1” when input signal isgreater than the reference signal or “0” when the input signal is lessthan the reference signal. Here the outputs are, respectively, 0, 1, 1.The logic circuit 180 converts the binary output signals into a binarynumber for dividing the input frequency. A truth table of the possiblebinary output signals looks as follows: A B C N(decimal) 0 0 0 0 0 0 1 10 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7

[0049] The combinational logic, as just described, converts the resultsof the comparator signals into a decimal number. Suitable logic providesan output integer divisor signal that is greater than 1 and less than 8.The input frequency is divided by the divisor to generate a class Doscillator signal that does not interfere with the AM signal. Here the011 results in a divisor of 3 and the input frequency is divided from1200 kHz to 400 kHz.

[0050] Those skilled in the art understand that the combinational logiccircuit can be configured to provided different divisors depending uponthe range of input frequencies. The comparator outputs may be combinedwith AND, OR, NOR or XNOR logic gates to achieve practical results. Theabove example is presented merely to show a simple logic circuit.

[0051] Digital Comparators

[0052] A method for using the AM local oscillator (LO) as a clock sourcefor a class D amplifier is shown in FIG. 5. A square wave LO 100, alongwith a low-frequency reference clock frequency 110, serve as inputs to atwelve bit counter and latch circuit 120. If the AM tuner's LO is not asquare wave, those skilled in the art can understand that a simpleanalog circuit can be constructed to convert it to a square wave. Thetwelve bit counter accumulates pulses from the LO during the period ofthe much slower reference clock. When the reference clock period ends,the most significant eight bits of the counter are latched to the outputof the module 120. The least significant four bits of the counter outputare discarded as they serve only to help filter the counter value.

[0053] The eight bit latched counter value 130 serves as an input tothree digital magnitude comparators 140-142. The magnitude comparatorscompare three different reference values 150, 160, 170 to the latchedcounter value 130. Those skilled in the art understand that themagnitude comparators can be made many different ways. One possible wayis to cascade two type 7485 digital four bit comparators for each eightbit comparator. It is also desirable to have hysteresis built into eachcomparator to prevent noise at boundary conditions from causing anyinstability in the comparators' 140-142 outputs.

[0054] The reference values 150, 160, and 170 correspond to frequenciesat which the value of N should change. The reference values aredetermined based on a special algorithm and the ratio of the localoscillator frequency 100 to the reference clock frequency 110. N can bean integer between the values of three and six inclusive. Each eight bitmagnitude comparator has three outputs 180 that indicate whether thereference value 150, 160, or 170 is less than, equal to, or greater thanthe latched counter value 130. All three comparators' three outputs 180serve as inputs to a filter circuit 190 which feeds combinational logic200 that sets a three bit value of N 210 based on the comparators'filtered outputs. Those skilled in the art understand that thecombinational logic block 200 and filter circuit 190 can be designedwith many different logic devices including AND, NAND, OR, and NORgates.

[0055] A divide-by-N circuit 220 takes the value of N 210 and the squarewave LO input 100 and divides the LO input 100 by N 210. Thedivided-down LO 230 is the output from the divide-by-N circuit 210.Those skilled in the art understand that the divide-by-N circuit can becreated in many different ways, including using integrated circuitdivide-by-N logic devices, other off-the-shelf logic products, orgate-level designs. The divided-down LO 230 is a fixed frequency squarewave dependent upon the frequency of the LO 100. The divided-down LO 220is used to control the frequency of an attached class D amplifier.

[0056] Here is an example of how the circuit and method works to providea class D oscillator signal that does not interfere with an input AMsignal. Assume the AM oscillator is at a frequency of 1200 kHz. The 12bit counter 120 counts pulses from the AM local oscillator 100 over afixed time period. The most significant eight bits of the count tallyare periodically latched to the output 130 of the counter and latch 120.Assume that the output of the counter and latch 120 is “200.” The “200”is latched as the eight most significant bits to provide an input signalto the three comparators 140, 141, 142. Each comparator stores orreceives a reference number, A, B, and C, respectively. The referencenumbers correspond to frequency breakpoints for AM signals in the980-2160 kHz range of input local oscillator signals. For example,reference A might be “220”, reference B is “150” and reference C is“100”. The comparators 140-142 output a two bit binary signalrepresentative of whether the input is greater than, less than or equalto the reference number. For example, the comparators have a binaryoutput of “010” when the input signal is greater than the referencesignal, “001” when the input signal is less than the reference signal,and “100” when the input equals the reference. The logic circuit 180converts the binary output signals of the comparators into a binarynumber for dividing the input frequency.

[0057] The differences between the reference numbers are chosen tocorrespond to a desired range of frequencies. For example, a numbergreater than A may correspond to a frequency above 1800 kHz; between Aand B may correspond to 1500-1800 kHz; 1200-1500 corresponds to a numberbetween B and C and any number less than C corresponds to a frequencyless than 1200 kHz. Such a choice establishes the algorithm forselecting the number N that divides the AM local oscillator frequency.For example, a frequency in the range of less than 1200 kHz will bedivided by 3 to keep the resulting switching frequency far away from 450kHz or any harmonics thereof.

[0058] The combinational logic converts the results of the comparatorsignals into a decimal number. Suitable logic provides an output integerdivisor signal that is greater than 1 and less than 8. The inputfrequency is divided by the divisor to generate a class D oscillatorsignal that does not interfere with the AM signal. Here the 011 resultsin a divisor or 3 and the input frequency is divided from 1200 kHz to400 kHz.

[0059] Those skilled in the art understand that the combinational logiccircuit can be configured to provided different divisors depending uponthe range of input frequencies. The comparator outputs may be combinedwith AND, OR, NOR or XNOR logic gates to achieve practical results. Theabove example is presented merely to show a simple logic circuit.

[0060] Two Loop Comparator

[0061]FIG. 6 shows an AM radio local oscillator (LO) signal 600 that isinput to the algorithm. It passes through a divide-by-N circuit thatdivides the frequency of the LO by the integer value N where N isbetween the values of 3 and 6 inclusively. The divided-down localoscillator 620 is the output from the circuit. Those skilled in the artunderstand that the divide-by-N circuit can be created in many differentways, including using integrated circuit divide-by-N logic devices,other off-the-shelf logic products, or gate-level designs. Thedivided-down LO 620 is a fixed frequency square wave dependent upon thefrequency of the LO 600. The divided-down LO 620 is used to control thefrequency of an attached class D amplifier.

[0062] The value of N is determined by two frequency comparator circuitsoperating as feedback controllers. One comparator 630 compares thedivided down LO with a maximum frequency “ceiling” that has beenpredetermined based on a desired maximum operating frequency and theamount of separation between switching harmonics and tuned radiostations that the ceiling provides. If the divided down LO frequency isabove that ceiling, the value of N is increased. By increasing N, thefrequency of the divided down LO will decrease. The ceiling comparator630 will keep increasing N until the divided down LO is at or below thefrequency ceiling. When the divided down LO falls below the frequencyceiling, the ceiling comparator 630 no longer increases N. As long asthe frequency ceiling is properly chosen, N will be at its maximum valueof six when the local oscillator is at its maximum frequency of 2260kHz. The frequency ceiling for one particular class D amplifier is 360kHz. 360 kHz provides for the best possible switching harmonicseparation from the tuned radio station while keeping switching suitablefor at least one particular class D amplifier design.

[0063] The just-described feedback loop only increments N. If the userof the AM radio is tuning down the AM band and there was no mechanism todecrease the value of N, the divided-down LO would drop to such a lowfrequency that the attached class D amplifier would be switching tooslowly for its output filters to adequately remove the switchingfrequency and its harmonics from its output. In addition, N would not beat its correct value for avoiding AM radio interference. Therefore, amechanism for resetting N to its lowest value of three has been devised.The feedback loop 640 that resets N runs in parallel with the ceilingcomparator 630 feedback loop.

[0064] The N-reset feedback loop 640 stores a recent LO frequency valuein a memory such as a digital counter. The loop compares the current LOfrequency to the one stored in its memory. If the new frequency is lowerthan the old frequency, the user is tuning the AM radio from a higher toa lower frequency station. Such a change will reset N to its lowestvalue of three. If that value of N is then too low for the newly tunedstation, the ceiling comparator will detect that problem and increase Nappropriately.

[0065] Multiple Clocks

[0066] A method for using the AM local oscillator (LO) as a determinantof clock frequency for a class D amplifier controller is shown in FIG.7. A square wave LO 100, along with a low-frequency reference clock 110,serve as inputs to a twelve bit counter and latch circuit 120. If the AMtuner's LO is not a square wave, those skilled in the art understandthat a simple circuit can be constructed to convert it to a square wave.The twelve bit counter accumulates pulses from the LO during the periodof the much slower reference clock. When the reference clock periodends, the most significant eight bits of the counter are latched to theoutput of the module 120. The least significant four bits of the counteroutput are discarded as they serve only to help filter the countervalue.

[0067] The eight bit latched counter value 130 serves as an input tothree digital magnitude comparators 140-142. The magnitude comparators140-142 compare three different reference values 150, 160, 170 to thelatched counter value 130. Those skilled in the art understand that themagnitude comparators 140-142 can be made many different ways. Onepossible way is to cascade two type 7485 digital four bit comparatorsfor each eight bit comparator 140-142. It is desirable to havehysteresis built into each comparator, or use filtering 190 after thecounters, to prevent noise at count values near window comparatortransition points from causing any instability in the comparators'140-142 outputs.

[0068] The reference values 150, 160, and 170 correspond to frequenciesat which the controller should toggle between different oscillatorfrequencies. The reference values are determined based on a specialalgorithm and the ratio of the local oscillator frequency 100 to thereference clock frequency 110.

[0069] The logic block 200 is used to determine which externaloscillator 220 should be activated by electronic switch 210. If theoutput oscillator 220 frequencies are correctly picked and the referencefrequencies 150 at which they are engaged are properly chosen, theresultant output frequency 230 that is driving the class D amplifierwill always produce a switching frequency and harmonics that avoid thetuned AM radio station.

[0070] Other Applications

[0071] Those skilled in the art will appreciate that the invention maybe applied to any switching amplifier where harmonics are a problem. Forexample, the invention is useful in power supplies. As the demand formore efficient power supplies increases, switching amplifiers areleading candidates for the most efficient power supply. The structureand operation of a switching power supply are substantially the same asa class D audio amplifier. Likewise, switching amplifiers generateunwanted AM harmonics. The invention can be readily incorporated intoswitching power supplies to solve the problem of unwanted AM harmonics.

[0072] Having thus described the preferred embodiments and applicationsof the invention, those skilled in the art will understand that furtheradditions, changes and modifications may be made to the inventionwithout departing from the spirit and scope as set forth in thefollowing claims.

1. A circuit for avoiding AM radio interference in a class D amplifier,said circuit comprising: means for comparing a first signalrepresentative of a frequency of an AM signal to one or more referencesignals representative of different frequencies, and for generatingcomparator signals representative of whether the first signal is greaterthan, less than or equal to the reference signals; means for issuing afrequency divisor signal dependent at least in part upon said comparatorsignals, said frequency divisor signal representative of a frequencydivisor number; and means for generating an oscillator signal for theclass D amplifier, said oscillator signal having a switching frequencyderived by dividing the frequency of the AM signal by said frequencydivisor number.
 2. The circuit of claim 1, wherein the AM signal is alocal oscillator signal.
 3. The circuit of claim 1, wherein saidreference signals and said first signal are digital signals, said meansfor comparing comprising a counter and latch circuit, said counter andlatch circuit receiving the AM signal and a reference clock signal, saidcounter and latch issuing said first signal.
 4. The circuit of claim 3,wherein said means for comparing further comprises at least one digitalcomparator circuit, each of said comparator circuits comparing saidfirst signal to a corresponding one of said reference signals, each ofsaid comparator circuits generating a respective one of said comparatorsignals.
 5. The circuit of claim 3, wherein said means for issuing afrequency divisor signal comprises a logic circuit receiving saidcomparator signals and issuing said frequency divisor signal.
 6. Thecircuit of claim 5, said means for issuing a frequency divisor signalfurther comprising at least one filter, each filter receiving acorresponding one of said comparator signals and issuing filteredcomparator signals to said logic circuit.
 7. The circuit of claim 1,wherein said means for generating an oscillator signal comprises adivider circuit, said divider circuit receiving said divisor signal andthe AM signal, and issuing said oscillator signal.
 8. The circuit ofclaim 1, wherein said reference signals and said first signal are directcurrent (DC) signals, said means for comparing comprising a filter, saidfilter receiving the AM signal and issuing said first signal.
 9. Thecircuit of claim 8, wherein said means for comparing further comprisesat least one analog comparator, each of said comparators comparing saidfirst signal to a corresponding one of said reference signals, each ofsaid comparators generating a respective one of said comparator signals.10. The circuit of claim 8, wherein said means for issuing a frequencydivisor signal comprises a logic circuit receiving said comparatorsignals and issuing said divisor signal.
 11. The circuit of claim 1,wherein said frequency divisor number comprises an integer divisorgreater than one and less than
 8. 12. A circuit for avoiding AM radiointerference in a class D amplifier, said amplifier having an oscillatorsignal, said oscillator signal having a switching frequency, saidcircuit comprising: means for converting an AM signal into a firstsignal, said first signal dependent at least in part upon a frequency ofsaid AM signal; means for comparing said first signal to one or morereference signals, said means for comparing issuing comparator signals,said comparator signals being representative of whether said firstsignal is greater than, less than or equal to said reference signals;means for issuing a frequency divisor signal dependent at least in partupon said comparator signals, said frequency divisor signalrepresentative of a frequency divisor number; and means for modifyingsaid switching frequency to a divided switching frequency, said dividedswitching frequency being dependent at least in part upon the frequencyof the AM signal and said frequency divisor number.
 13. The circuit ofclaim 12, wherein the AM signal is a local oscillator signal.
 14. Thecircuit of claim 12, wherein said reference signals and said firstsignal are digital signals, said means for converting comprising acounter and latch circuit, said counter and latch circuit receiving theAM signal and a reference clock signal, said counter and latch issuingsaid first signal.
 15. The circuit of claim 14, wherein said means forcomparing comprises at least one digital comparator circuit, each ofsaid comparator circuits comparing said first signal to a correspondingone of said reference signals, each of said comparator circuitsgenerating a respective one of said comparator signals.
 16. The circuitof claim 15, wherein said means for issuing a frequency divisor signalcomprises a logic circuit receiving said comparator signals and issuingsaid frequency divisor signal
 17. The circuit of claim 16, wherein saidmeans for issuing a frequency divisor signal further comprises at leastone filter, each filter receiving a corresponding one of said comparatorsignals and issuing filtered comparator signals to said logic circuit.18. The circuit of claim 12, wherein said reference signals and saidfirst signal are analog signals, said means for converting comprising afilter circuit, said filter circuit receiving the AM signal and issuingsaid first signal.
 19. The circuit of claim 18, wherein said means forcomparing comprises at least one analog comparator circuit, each of saidcomparator circuits comparing said first signal to a corresponding oneof said reference signals, each of said comparator circuits generating arespective one of said comparator signals.
 20. The circuit of claim 12,wherein said means for modifying said switching frequency comprises adivider circuit receiving said divisor signal and the AM signal, andissuing said divided switching frequency, said divided switchingfrequency derived by dividing the frequency of the AM signal by saidfrequency divisor number
 21. The circuit of claim 12, further comprisinga plurality of oscillator circuits, each of said oscillator circuitsissuing an oscillator signal having a respective switching frequency,said means for modifying said switching frequency comprising a logic andswitching circuit interconnected between said means for comparing andsaid oscillator circuits, said logic and switching circuit receivingsaid comparator signals and selecting dependent at least in part thereonone of said oscillator circuits.
 22. The circuit of claim 12, whereinsaid frequency divisor number comprises an integer divisor greater thanone and less than
 8. 23. A method for avoiding AM radio interference ina class D amplifier, said amplifier having an oscillator signal, saidoscillator signal having a switching frequency, said method comprisingthe steps of: converting an AM signal into a first signal representativeof the frequency of the AM signal; comparing said first signal to one ormore reference signals; determining dependent at least in part upon saidcomparing step a modified switching frequency for the oscillator signal;and issuing the oscillator signal at the modified switching frequency tothereby avoid interference with the AM signal.
 24. The method of claim23, wherein said issuing step comprises selecting one of a plurality ofoscillators, each of said oscillators having a respective switchingfrequency.
 25. The method of claim 23, wherein said comparing stepfurther comprises issuing comparator signals, each of said comparatorsignals being representative of whether the first signal is greaterthan, less than or equal to a corresponding one of said referencesignals;
 26. The method of claim 25, comprising the further step ofgenerating a frequency divisor number dependent at least in part uponsaid comparator signals.
 27. The method of claim 26, wherein saiddetermining step comprises dividing the frequency of the AM signal bythe frequency divisor number to derive the modified switching frequency.28. The method of claim 23, wherein the AM signal is a local oscillatorsignal.
 29. The method of claim 23, wherein said reference signalscomprise binary signals, and said converting step comprises convertingthe AM signal into a binary signal.
 30. The method of claim 29,comprising the further step of filtering the comparator signals prior tosaid selecting step.
 31. The method of claim 23, wherein said referencesignals comprise analog signals, and said converting step comprisesconverting the AM signal to a direct current (DC) signal.
 32. The methodof claim 31, wherein the converting step comprising filtering the AMsignal.
 33. A method for avoiding AM radio interference in a class Damplifier comprising: dividing the frequency of an AM signal by aninteger divisor to generate a divided oscillator signal for the class Damplifier that does not interfere with the AM signal; iterativelycomparing the frequency of the divided oscillator signal to a referencefrequency; incrementing the integer divisor when the divided oscillatorsignal is greater than the reference frequency; iteratively comparing acurrent frequency of the AM signal to a previous frequency of the AMsignal; and resetting the integer divisor to a minimum integer when thecurrent frequency of the AM signal is less than the previous frequencyof the AM signal.
 34. The method of claim 33, wherein the AM signalcomprises a local oscillator signal.
 35. The method of claim 34, whereinthe local oscillator varies over a range of 980 kHz to 2260 kHz.
 36. Themethod of claim 33, wherein the minimum integer is 3 and the value ofthe integer varies from 3 to 6 inclusively.
 37. A circuit for avoidingAM radio interference in a class D amplifier, comprising: a divide by Ncircuit receiving an input local oscillator signal having an inputfrequency, said divide by N circuit issuing a divided local oscillatorsignal having a divided frequency that does not interfere with the localoscillator signal, said divided frequency being derived by dividing saidinput frequency by an integer divisor; a first comparator receiving thedivided local oscillator signal and comparing the divided frequency to areference frequency, said first comparator issuing an increment signalwhen said divided local oscillator signal is greater than said referencesignal; an incrementing circuit receiving said increment signal andincrementing said integer divisor in response thereto; a secondcomparator receiving said input local oscillator signal and comparingsaid input frequency to a previous value of said input frequency, saidcomparator issuing a reset signal when said input frequency is less thansaid previous value; and a reset circuit receiving said reset signal andresetting said integer divisor to a minimum integer in response thereto.38. The circuit of claim 37, wherein said input oscillator frequencyvaries from approximately 980 kHz to approximately 2260 kHz.
 39. Thecircuit of claim 37, wherein the minimum integer is 3 and the value ofthe integer varies from 3 to 6 inclusively.